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| C8051F067 25 MIPS, 32 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals Two 16-Bit ADCs High-Speed 8051 C Core - - 0.75 LSB INL; no missing codes Programmable throughput up to 1 Msps (each ADC) 1 external input each; programmable as two single-ended or one differential ADC DMA to XRAM or external memory interface Data-dependent windowed interrupt generator 16 programmable hysteresis values Configurable to generate interrupts or reset Pipe-lined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler 4352 bytes data RAM 32 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) 24 port I/O; all are 5 V tolerant Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timers or PCA Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Typical operating current: 18 mA at 25 MHz Multiple power saving sleep and shutdown modes Memory Three Comparators Digital Peripherals Internal Voltage Reference Precision VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Clock Sources Supply Voltage: 2.7 to 3.6 V 64-Pin TQFP Temperature Range: -40 to +85 C VDD VDD VDD DGND DGND DGND AV+ AGND Digital Power Analog Power TCK TMS TDI TDO RST MONEN XTAL1 XTAL2 JTAG Logic Boundary Scan Debug HW Reset 8 0 5 1 C o r e UART0 UART1 SMBus SPI Bus PCA P0 Drv P0.0 P0.7 P1.0/AIN2.0 P1.7/AIN2.7 VDD Monitor External Oscillator Circuit 25 MHz 2% Internal Oscillator WDT SFR Bus Timers 0, 1, 2,3,4 P0, P1, P2, P3 Latches C R O S S B A R P1 Drv P2 Drv P2.0 P2.7 System Clock 32 kB FLASH 256 Byte RAM 4 kB RAM CP1 CP2 P3 Drv VREF VREF CP0 + + + - P2.6 P2.7 P2.2 P2.3 P2.4 P2.5 AVDD ADGND AV+ AGND VREF0 VRGND0 AIN0 AIN0G VBGAP0 CNVSTR0 AVDD ADGND AV+ AGND VREF1 VRGND1 AIN1 AIN1G VBGAP1 CNVSTR1 ADC0 1 Msps (16-Bit) R E S U L T 0 External Data Memory Bus P4 Latch Ctrl Latch P5 Latch Addr15-8 P6 Latch Addr7-0 P7 Latch Data Latch P4 DRV P5 DRV P6 DRV P7 DRV ADC1 1 Msps (16-Bit) R E S U L T 1 + - D I F F DMA EMIF Cntrl Precision Mixed Signal Copyright (c) 2004 by Silicon Laboratories 7.28.04 C8051F067 25 MIPS, 32 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 25 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range 16-BIT A/D CONVERTERS Resolution Integral Nonlinearity Single-ended Mode Differential Mode Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Fin = 10 kHz, Single-ended Distortion Fin = 10 kHz, Differential Total Harmonic Distortion Fin = 10 kHz, Single-ended Fin = 10 kHz, Differential Spurious-Free Dynamic Fin = 10 kHz, Single-ended Range Fin = 10 kHz, Differential Throughput Rate Input Voltage Range Single-ended (AINn-AINnG) Differential (AIN0-AIN1) Power Supply Current Operating Mode, 1 Msps (each ADC) (AVDD + AV+) Shutdown Mode MIN 2.7 TYP MAX 3.6 UNITS V mA mA A A MHz bits LSB LSB LSB dB dB dB dB dB dB Msps V V mA A 18 0.7 20 0.1 DC 16 0.75 0.50 0.5 86 89 96 103 97 104 0 -VREF 5.5 1 25 2 1 1 1 VREF VREF Package Information D D1 C8051F060DK Development Kit MIN NOM MAX (mm) (mm) (mm) A - - 1.20 0.15 1.05 A1 0.05 E1 E A2 0.95 b 0.17 0.22 0.27 12.00 10.00 0.50 12.00 10.00 - 64 PIN 1 DESIGNATOR 1 A2 e A b A1 D D1 e E E1 Precision Mixed Signal Copyright (c) 2004 by Silicon Laboratories 7.28.04 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
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